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FINN+ is a powerful framework for deploying quantized neural networks on FPGA hardware. It specifically targets quantized neural networks (QNNs), with emphasis on generating dataflow-style architectures customized for each network.
This Wiki is currently being updated for FINN+ 1.4.0. Some information may be oudated!
FINN+ takes your quantized neural networks (in QONNX format) and automatically generates optimized FPGA implementations. Whether you're targeting Zynq SoCs or Alveo data center cards, FINN+ handles the complex hardware generation process for you.
FINN+ is a fork of AMD's FINN framework and is developed as part of the EKI research project. For additional information on the original FINN framework, we refer to the project website: https://xilinx.github.io/finn/
- 🔄 Automated Compilation - From ONNX model to FPGA bitstream
- ⚡ High Performance - Optimized dataflow architectures
- 🎛️ Flexible Configuration - Fine-tune performance vs. resource trade-offs
- 📊 Resource Estimation - Predict FPGA utilization before synthesis
- 🔧 Multiple Targets - Support for Zynq and Alveo platforms
- 🐍 PYNQ Integration - Python driver for rapid prototyping
- ⚡ High-Performance C++ - Optimized C++ driver for production deployment
Check out our Quick-start guide page to get started immediately!
This wiki is split by audience. Where to Start routes you to the right path.
| Page | Description |
|---|---|
| Quick Start & Installation | Get FINN+ running |
| How a Build Works | What the compiler does to your model |
| Preparing Your Model | Exporting from Brevitas |
| Building an Accelerator | Configuring and running a build |
| Folding | Trading resources for throughput |
| Deployment | Getting the design onto hardware |
| DataflowBuildConfig | Complete configuration reference |
| Page | Description |
|---|---|
| Development Guide | Environment setup, linting, testing, PR conventions |
| Implementation Details | The IR, ModelWrapper, core concepts |
| Analysis Passes | Inspecting a model |
| Transformations and Steps | Changing a model |
| Custom Operations | Adding operators and hardware layers |
| API Documentation | Generated module reference |
- Image classification on edge devices
- Real-time object detection
- Video processing pipelines
- Audio classification and enhancement
- Sensor data processing
- Time-series analysis
- Predictive maintenance
- Quality control systems
- Process optimization
These are FINN+'s top level commands. To learn how they are used, simply run them with the --help flag.
| Command | Description |
|---|---|
finn build <config> [<model>] |
Build FPGA accelerator from ONNX model |
finn run <flow_file> |
Run custom build flow (legacy) |
finn settings |
Manage your FINN+ settings |
finn deps |
Manage FINN+'s dependencies |
finn wizard |
Get assistance with setting up FINN+ |
finn test |
Run a test suite |
- 📖 Documentation: This wiki contains comprehensive guides
- 🐛 Issues: Report bugs on GitHub
- 💬 Discussions: Join the community discussions
- 🔧 Contributing: See our Development guide
- Brevitas - Quantization-aware training library
- QONNX - Quantized ONNX representation
- PYNQ - Python framework for FPGA acceleration
Ready to get started? 👉 Begin with the Quick Start Guide & Installation, or browse the Tutorials
🏠 Home
Using FINN+ to compile a network.
Getting started
Building
Tuning
Checking
Reference
Working on the FINN+ compiler itself.
Getting started
Extending FINN+
Compiler internals
- Network Preparation
- Hardware Build
- Folding
- FIFO Sizing
- Multi-Layer Offload
- Simulation & Verification
Testing
Reference
- FINN+ Repository
- Brevitas - Quantization library
- QONNX - Model format
- finn-examples - Pre-built accelerators