SAFARI Research Group at ETH Zurich and Carnegie Mellon University
- 969 followers
- ETH Zurich and Carnegie Mellon University
- https://safari-research.org/
- omutlu@gmail.com
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Repositories
- HBM-Power Public
An accurate power model for high bandwidth memory (HBM) building on detailed power consumption characterization of 36 real HBM2 stacks. See our paper for more details https://arxiv.org/pdf/2610.14244.
- ramulator2 Public
Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our IEEE CAL 2023 paper: https://arxiv.org/pdf/2308.11030.
- MORDOR Public
MORDOR is an elastic memory scheduling mechanism to improve performance and energy consumption of memory controller-based read disturbance mitigation, as described in the MICRO 2026 paper by Makeenkova et. al.
- Chronus Public
Chronus is an on-DRAM-die read disturbance mitigation mechanism that addresses the two major weaknesses of the new industry standard Per Row Activation Counting (PRAC) by eliminating counter update latency and preventing the wave attack. Described in the HPCA 2025 paper: https://arxiv.org/abs/2502.12650
- Virtuoso Public
Virtuoso is a fast, accurate and versatile simulation framework designed for virtual memory research. Virtuoso uses a new simulation methodology for estimating OS overheads and models diverse VM designs, incorporating state-of-the-art TLB techniques, page table structures etc. More details in our ASPLOS 2025 paper: https://arxiv.org/pdf/2403.04635
- Terracotta Public
A flexible memory control framework to reduce the repeated DRAM interface and controller modifications required by DRAM techniques via custom DRAM command extensions and a programmable memory controller, as described in the MICRO 2026 paper by Songara et al.
- Hermes Public
A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical path, as described by MICRO 2022 paper by Bera et al. (https://arxiv.org/pdf/2209.00188.pdf)
