Repository navigation
RVY libunwind patches. - #832
Conversation
Stop treating the trusted stack pointer as a register because it is unnecessary and some architectures like RISC-V do not in fact store it in a dedicated register. Co-authored-by: Dapeng Gao <dapeng.gao@cl.cam.ac.uk>
| CHERI_DBG("C18N: SET IP: %#p\n", state.pc); | ||
|
|
||
| #ifdef _LIBUNWIND_TARGET_AARCH64 | ||
| static constexpr int callee_saved[] = { |
There was a problem hiding this comment.
LLVM style is lowerCamelCase. Also ideally this would be split into one commit that pulls out calleeSaved and then another that ifdefs to add a RISC-V one.
There was a problem hiding this comment.
:( did not double check for this, will fix.
There was a problem hiding this comment.
still needs a clang-format pass
| .macro restore_fpr num, ctxreg | ||
| #ifdef __CHERI_PURE_CAPABILITY__ | ||
| fld f\num, (RISCV_FOFFSET + RISCV_FSIZE * \num)(c\ctxreg) | ||
| fld f\num, (RISCV_FOFFSET + RISCV_FSIZE * \num)(\ctxreg) |
There was a problem hiding this comment.
Please split the RVY-compatible mnemonic changes out from the c18n changes
There was a problem hiding this comment.
Also at this point the ifdef isn't needed? Nor are the GPR ones needed, so long as ILOAD/ISTORE/RISCV_ISIZE are appropriately renamed to not be I for Integer, and defined to be LY/SY/__SIZEOF_CHERI_CAPABILITY__ CHERI?
Edit: Meant to include this in the original review but it was left pending... so will just do this myself :)
There was a problem hiding this comment.
Should be fixed now.
bfa2298 to
6aa420d
Compare
dpgao
left a comment
There was a problem hiding this comment.
All good except some indentation issues.
Co-authored-by: Dapeng Gao <dapeng.gao@cl.cam.ac.uk>
6aa420d to
50313f2
Compare
jrtc27
left a comment
There was a problem hiding this comment.
Thanks. I will follow up with some simplification of the (save|restore)_[gf]pr macros.
| .macro restore_fpr num, ctxreg | ||
| #ifdef __CHERI_PURE_CAPABILITY__ | ||
| fld f\num, (RISCV_FOFFSET + RISCV_FSIZE * \num)(c\ctxreg) | ||
| fld f\num, (RISCV_FOFFSET + RISCV_FSIZE * \num)(\ctxreg) |
There was a problem hiding this comment.
Also at this point the ifdef isn't needed? Nor are the GPR ones needed, so long as ILOAD/ISTORE/RISCV_ISIZE are appropriately renamed to not be I for Integer, and defined to be LY/SY/__SIZEOF_CHERI_CAPABILITY__ CHERI?
Edit: Meant to include this in the original review but it was left pending... so will just do this myself :)
16abc1d, for posterity |
These enable c18n on RVY.