Docs: mhpmevent reset values in performance_counters.rst do not match RTL (1 << i vs 1 << (i-3)) #2550

Observed Behavior

The mhpmevent reset values documented in doc/03_reference/performance_counters.rst do not match what the RTL returns on a CSR read.

The selector table (performance_counters.rst#L128-L153) lists mhpmevent3 = 0x0000_0008, mhpmevent4 = 0x0000_0010, ..., mhpmevent12 = 0x0000_1000, i.e. bit i set for mhpmeventi. Lines 52-53 also say a set bit selects "events with this ID".

The RTL hardwires the selectors as (ibex_cs_registers.sv#L1606-L1607, with MHPMCOUNTER_BASE = 3 at L184):

mhpmevent[i][i - MHPMCOUNTER_BASE] = 1'b1;

and the CSR read returns this value directly (L575). So mhpmevent3 reads 0x1, mhpmevent4 reads 0x2, ..., mhpmevent12 reads 0x200.

The DV models agree with the RTL, not the doc: dv/cs_registers/model/register_model.cc expects 0x1 << (i - 3) (L48), and dv/cosim/spike_cosim.cc sets CSR_MHPMEVENT3 + i to 1 << i (L594-L598).

History: the original RTL used mhpmevent[i][i], which matched the table. #1748 (e53a02a, "Alter some CSR WARL behaviour to match spike") changed the RTL and the register model to 1 << (i - 3), but the doc table was not updated (it was also unchanged in #2484).

Counting itself is unaffected: the selectors are hardwired and the counters are wired to their events by index (L1587-L1596). The impact is limited to software that follows the doc to decode or check mhpmevent values; it would see event IDs offset by 3.

Expected Behavior

The doc and the RTL agree. Since the RTL, register model and Spike cosim all use 1 << (i - 3) deliberately (#1748), I'd suggest a documentation-only fix: change the reset values in the table to 0x0000_0001 ... 0x0000_0200, and state that the selector for mhpmcounterX has bit X-3 set (rather than "bit = event ID").

Minor, related: the selector rows are labelled mhpmeventX(h), but no mhpmeventXh CSRs are implemented.

Happy to open a PR for the doc change if that direction is acceptable.

Steps to reproduce the issue

Found by reading the source at c0c0708: compare the table in doc/03_reference/performance_counters.rst (L128-L153) with rtl/ibex_cs_registers.sv (L575, L1600-L1617) and dv/cs_registers/model/register_model.cc (L48). The CSR test in CI (tb_cs_registers) checks the RTL against the 1 << (i - 3) model, so the RTL behaviour is the tested one. I have not re-run a simulation specifically for this report.

My Environment

EDA tool and version: N/A (source reading)

Operating system: N/A

Version of the Ibex source code: c0c0708 (master), no local changes.