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[doc] Fix mhpmevent reset values in performance counters doc - #2570
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SamuelRiedel
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Thanks! Just a few minor unrelated nits while we're at it.
| | ``mhpmevent12(h)`` | 0x32C | 0x0000_1000 | 12 | | ||
| +----------------------+-------------+-------------+--------------+ | ||
| +----------------------+-------------+-------------+----------+-----+ | ||
| | Event Selector | CSR Address | Reset Value | Event ID | Bit | |
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Should we just say "Value" instaed of "reset value" to not suggest this can be modified later?
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Fair point, I'll change it.
| +----------------------+-------------+-------------+----------+-----+ | ||
| | Event Selector | CSR Address | Reset Value | Event ID | Bit | | ||
| +======================+=============+=============+==========+=====+ | ||
| | ``mhpmevent3(h)`` | 0x323 | 0x0000_0001 | 3 | 0 | |
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The (h) should be removed here, no? We don't have an mhpmeventXh register.
| The event selector CSRs ``mhpmevent3`` - ``mhpmevent31`` define which of these events are counted by the event counters ``mhpmcounter3(h)`` - ``mhpmcounter31(h)``. | ||
| If a specific bit in an event selector CSR is set to 1, this means that events with this ID are being counted by the counter associated with that selector CSR. | ||
| The event selector CSRs are hardwired and writes to them are ignored. | ||
| Each implemented event selector CSR ``mhpmeventX`` has exactly one bit set, bit X-3, i.e., ``mhpmevent3`` reads as ``0x1``, ``mhpmevent4`` reads as ``0x2``, and so on. |
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Maybe add that it will read zero if not implemented.
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Thanks for your input @SamuelRiedel. All valid. Your points should be addressed now. |
Update the event selector table with the actual reset values and separate the event ID from the selector bit. Fixes lowRISC#2550, reported by WLHsu0827. Signed-off-by: Hakim Filali <hfilali@lowrisc.org>
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Great. Thanks a lot for this!
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Update the event selector table with the actual reset values and separate the event ID from the selector bit.
Fixes #2550, reported by WLHsu0827.